This invention relates to method and apparatus performing D/A (digital to analog) conversion functions, and more particularly to an integrated linear D/A converter circuit for converting a digital input word (corresponding to a binary number) to an analog output signal that is multiplied by a reference voltage V.sub.R and which is substantially insensitive to parasitic and stray capacitance effects associated with elements thereof.
D/A (and/or A/D) converters for converting a binary number consisting of ones and zeroes in a digital word to an analog voltage or current are described in the publications "A Monolithic Charge-Balanced Successive Approximation A/D Technique" by T. P. Redfern et al., IEEE Journal of Solid State Circuits, Vol. SC-14, No. 6, December 1979, pages 912-919; "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques--Part I" by Paul R. Gray et al., IEEE Journal of Solid State Circuits, Vol. SC-10, No. 6, December 1975, pages 371-379; and "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques--Part II" by Paul R. Gray, et al., IEEE Journal of Solid State Circuits, Vol. SC 10, No. 6, December 1975, pages 379-385, which are incorporated herein by reference. The conventional method of performing the D/A conversion is to add a number of voltages together, each voltage being weighted by the value of the corresponding bit position. In a multiplying D/A converter, an analog input voltage may provide a scale factor multiplying the output level. This conversion has previously been performed with precision ratioed current sources, binary integrated resistors, binary integrated capacitors, and ladder networks. Such arrangements require large numbers of precision components, e.g. one per bit in the digital input signal. Also, it is expensive to fabricate precision resistors in complementary metal oxide silicon (CMOS) technology. And CMOS current sources of precise ratios are difficult to fabricate. In an eight bit converter, for example, the total capacitance is at least 255 picofarads (since process constraints limit the smallest CMOS capacitor to around 1 picofarad), and requires a substantial surface area of a chip, the capacitor surface area doubling for each additional bit of a digital input word. Although the serial converter of Gray, et al. Part II requires only two unit valued capacitors, it is sensitive to parasitic capacitances associated with the switching transistors and the top plates of integrated capacitors. Techniques for compensating for parasitic capacitance effects in switched capacitor simulation circuits are described in the articles "Compensation for Parasitic Capacitances in Switched-Capacitor Filters" by G. C. Temes, et al., Electronics Letters, Vol. 15, June 21, 1979, pages 377-378; "Improved Circuit Eleents for Switched-Capacitor Ladder Filters" by M. S. Lee, Electronics Letters, Feb. 14, 1980, Vol. 16, No. 4, pages 131-133; and "Switched-Capacitor Filters Using Floating-Inductance Simulation Circuits" by M. S. Lee, Electronics Letters, Sept. 27, 1979, Vol. 15, Pages 644-645.
An object of this invention is the provision of an improved integratable D/A converter.